1. Field of the Invention
The present invention relates to a flip-flop circuit, and more particularly to a flip-flop circuit which is required to operate at high speed with low power consumption.
2. Description of the Related Art
Heretofore, a flip-flop circuit of the type described above is arranged as shown in FIG. 1 of the accompanying drawings.
As shown in FIG. 1, the flip-flop circuit has a pair of differential data input terminals 201, a normal-phase clock input terminal 202, an inverted-phase clock input terminal 203, a power supply 204, a pair of current sources 205, 206, a ground level 207, a pair of latch circuits 210, 211, and a pair of differential output terminals 212.
The differential data input terminals 201 are connected to respective differential signal input terminals of latch circuit 210. The normal-phase clock input terminal 202 and the inverted-phase clock input terminal 203, which serve as differential clock input terminals, are connected to respective differential clock input terminals of the latch circuits 210, 211. Specifically, the normal-phase clock input terminal 202 is connected to the normal-phase clock input terminal of latch circuit 210 and the inverted-phase clock input terminal of latch circuit 211, and the inverted-phase clock input terminal 203 is connected to the inverted-phase clock input terminal of latch circuit 210 and the normal-phase clock input terminal of latch circuit 211. The current sources 205, 206 are connected between current input terminals of the latch circuits 210, 211 and the ground level 207. Latch circuit 210 has differential signal output terminals connected to respective differential signal input terminals of latch circuit 211, whose differential signal output terminals are connected to the respective differential output terminals 212. The power supply 204 is connected between the ground level 207 and power supply input terminals of the respective latch circuits 210, 211.
Each of the latch circuits 210, 211 has a current mirror circuit 220, a current source 221, and a plurality of MOS transistors 222.about.227.
The differential signal input terminals, which are normal- and inverted-phase terminals, of latch circuit 210 are connected to the gates of MOS transistors 223, 222, respectively. The drain of MOS transistor 222 is connected to the gate of MOS transistor 224, the drain of MOS transistor 225, a first output terminal of the current mirror circuit 220, and one of the differential signal output terminals, which is an inverted-phase signal output terminal of latch circuit 210. The drain of MOS transistor 223 is connected to the gate of MOS transistor 225, the drain of MOS transistor 224, a second output terminal of the current mirror circuit 220, and the other of the differential signal output terminals, which is a normal-phase signal output terminal of latch circuit 210. MOS transistors 222, 223 have respective sources connected to the drain of MOS transistor 226, and MOS transistors 224, 225 have respective sources connected to the drain of MOS transistor 227. The gates of MOS transistors 226, 227 are connected to the inverted- and normal-phase clock input terminals, respectively, of latch circuit 210. The sources of MOS transistors 226, 227 are connected to the current input terminal of latch circuit 210. The current source 221 is coupled between an input terminal of the current mirror circuit 220 and the ground level 207. The power supply input terminal of the current mirror circuit 220 is connected to the power supply input terminal of latch circuit 210. Latch circuit 211 has the same circuit arrangement as latch circuit 210.
When the normal-phase clock input signal applied to latch circuit 210 is of a low level, input information supplied to the differential data input terminals 201 is written into the MOS transistors 222, 223 which are in a differential stage. When the normal-phase clock input signal applied to latch circuit 210 is of a high level, the information which has been written into the MOS transistors 222, 223 at the time the normal-phase clock input signal is of a low level is latched by the latch that is composed of MOS transistors 224, 225.
Since latch circuit 211 operates in the same manner as latch circuit 210, the latch circuits 210, 211 connected such that the normal- and inverted-phase clock input terminals of latch circuit 210 are connected respectively to the inverted- and normal-phase clock input terminals of latch circuit 211 can function as a flip-flop circuit.
The conventional flip-flop circuit has been disadvantageous in that the drains of MOS transistors 222, 223 in the differential stage of the first latch circuit 210 are connected to many loads, i.e., the output terminals of the current mirror circuit 220, the gates and drains of MOS transistors 224, 225, and the gates of the MOS transistors in the differential stage of the second latch circuit 211, imposing a limitation on high-speed operation of the flip-flop circuit. Another problem is that the power requirement of the flip-flop circuit is high because it has many current sources and a current flows at all times in the circuit.